Endpoint Security
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Geo Focus: The United Kingdom
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Geo-Specific
Program Director Mike Eftimakis on How to Fix 70% of Memory Safety Issues
A hardware security initiative backed by the British government is tackling one of the largest cybersecurity challenges: memory safety.
See Also: Strengthening Your Security Program With Open API
Capability Hardware Enhanced RISC Instructions – better known as CHERI – is a hardware method for limiting buffer overflow attacks. It embeds security into the processor’s core, enabling fine-grained memory access control and compartmentalization. Despite its name, backers say it also works on x86 chip architecture (see: UK Official Touts CHERI for Memory-Safe Computing).
The CHERI architecture addresses about 70% of today’s hackable vulnerabilities, said Mike Eftimakis, CHERI Alliance founding director. The alliance, founded in 2024 has the backing from the National Cyber Security Center, BT Group, SCI Semiconductor, Google and others.
Integrating CHERI into products requires updates across the entire electronics supply chain, so the alliance has been steadily expanding its work to promote adoption by chip designers, system integrators and open-source communities, Eftimakis said.
“We see a great interest by system company integrators,” he said. “The thing is that the electronic supply chain is a global supply chain. So, we also need to make sure that others are on board with that. And that’s also the reason why the alliance tries to reach internationally.”
In this video with Information Security Media Group, Eftimakis discusses:
- How CHERI addresses memory safety issues;
- Common hardware supply chain vulnerabilities;
- Progress on adoption by chipmakers;
- Scalability challenges associated with CHERI.
Eftimakis, who serves as vice president of strategy and ecosystem at Codasip, has over 30 years of experience in the electronics industry, having held senior technical and business roles at companies including VLSI Technology, NewLogic, Arm and Codasip.

